1. Field of the Invention
The present invention is generally in the field of electrical circuits. More particularly, the invention is in the field of phase locked loops.
2. Related Art
Phase locked loops that are implemented with digital circuitry provide various advantages, such as increased reliability and ease of integration, compared to analog phase locked loops. In a digital phase locked loop, a digitally controlled oscillator is used in place of a voltage controlled oscillator for signal generation. A digitally controlled oscillator does not require a varactor diode for tuning, which saves a processing step and reduces mask cost compared to a voltage controlled oscillator.
However, in order to achieve a sufficiently high dynamic range, a digital phase locked loop requires a digitally controlled oscillator with a sufficiently low gain. In a digitally controlled oscillator, attaining a desirably low gain can be reduced to the ability to digitally control very small amounts of capacitance. However, known approaches to achieving sufficiently low gain in a digitally controlled oscillator suffer from various undesirable drawbacks.
In one approach, capacitors having appropriately small capacitances are switched in and out of a tank circuit of a digitally controlled oscillator in an attempt to achieve low gain. However, the parasitic capacitances of the switches ultimately limits the above approach and results in a digitally controlled oscillator having undesirably high gain. In another approach, a digital delta-sigma modulator is used to re-quantize the least significant bits of a control word to achieve a low gain digitally controlled oscillator. However, the digital delta-sigma modulator approach requires a sampling rate of 600.0 MHz or higher, which undesirably increases power consumption.
Thus, there is a need in the art for a digitally controlled oscillator having an appropriately low gain without a concomitant increase in power consumption.